VHDL Physical Type is not Synthesizable, or is it?
Everybody who has been taught VHDL in college or in a company with senior colleagues has heard the following "wisdom":Pysical types are for simulation only. They cannot be synthesized. [commonly heard...
View ArticleVHDL Physical Type is not Synthesizable, or is it? (part 2)
In a previous post I pointed out that VHDL synthesis tools can indeed synthesize VHDL physical types. In the example I gave, all computations with physical types were done at elaboration time, so that...
View ArticleHow well does your compiler support VHDL 2008?
While some design teams will stick to VHDL-93 until the sun burns out, some people are using as much of the new VHDL-2008 standard as is supported by their tools. Big question is: how much is actually...
View ArticleWriting Finite State Machines
Write an entire case statement for your VHDL state machine with just a few key strokes. Use autocomplete (CTRL+SPACE) to generate an entire case statement. Then use CTRL+Click to jump from one state to...
View ArticleNo VHDL Plugin for IE or Chrome
There is no VHDL plugin for IE or Chrome. Not because it is not possible, but because there is no reason. There are two important points we’d like to make on this April Fools day:No need for a single...
View ArticleSet up your code generator in Sigasi
In many projects, some of the VHDL code is generated in one way or another. For instance, many projects manage their register map in one master file and generate their VHDL packages and C headers using...
View Article"Use" and "Library" in VHDL
Beginning VHDL engineers, and advanced engineers too, can get confused about the exact scope of a use clause and a library clause in VHDL. They usually show up at the top of a file, which would make...
View ArticleTo "to" or to "downto"... Ranges in VHDL
Most VHDL designers write 'something downto something' in their code all the time. But what does this downto actually mean. And what is the difference with to?The keywords downto and to specify the...
View ArticleBe careful with VHDL operator precedence
I was recently writing some tests for our VHDL expression evaluator and was amazed by the the result of evaluting -16 ** 2. I expected 256, but it wasn't.Can you guess the output of running this...
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